There have conventionally been CDR (Clock and Data Recovery) circuits which perform sampling of reception data, by synchronizing the phase of clock signals with the phase of reception data, so as to recover the data and clock.
Examples of CDR circuits include a 1x type CDR circuit which performs sampling of each bit of received data once, and a 2x type CDR circuit which performs sampling of each bit of received data twice.
Japanese Laid-open Patent Publication Nos. 2002-300142 and 2-111130 discuss the above related art.
Now, with conventional CDR circuits, multiple clock signals with different phases are used to perform sampling twice or more on each bit of received data.
Generating multiple clock signals with different phases has a problem in that the circuit becomes complex, and electric power consumed by the circuit increases.
Thus, there is a problem with conventional CDR circuits in that it is difficult to raise the sampling rate without increasing the number of clock signals.